1. Field of the Invention
The present invention relates to methods for making solid state devices and, more particularly, to methods for making an overlapping electrode structure on an insulation layer as used in solid state devices.
2. Description of the Prior Art
Recent developments in the art of solid state electronic devices have created a need for a method of making an overlapping electrode structure on an insulation layer such that the gap between adjacent electrodes on the insulation layer is limited to improve the performance of the solid state device. As a typical example, electrical gaps between adjacent electrodes as used in a charge couple device will cause the formation of surface potential barriers in the CCD semiconductor material that will inhibit the transfer of charge between adjacent potential wells of the CCD. By minimizing the gap between the adjacent electrodes, the potential barriers between the adjacent potential wells are limited, thereby improving the response and noise figure of the device. Other applications for the overlapping electrode structure will also occur to those skilled in the pertinent art.
In the prior art, methods have been developed for forming overlapping electrode structures that have been more or less effective in realizing the objective of limiting the effective electrical gap between adjacent electrodes. However, it was appreciated that methods that could diminish the effective electrical gap established by electrode structures made in accordance with methods known in the prior art could further improve the performance of the solid state devices in which they were used. Also, it was appreciated that more efficient methods of providing the overlapping electrode structure could improve the cost effectiveness of the solid state devices for which they were employed.
In this respect, it is further noted that recent developments in solid state electronic devices have created a need for making an overlapping electrode structure on a sloped insulator layer overlaying a semiconductor wafer. For example, a sloped oxide charge couple device has been investigated having improved transfer times between adjacent potential wells. The improved response times of the sloped oxide charge couple device are a consequence of the sloped disposition of the electrodes with respect to the interface of the semiconductor wafer and the insulation layer. This sloped disposition provides a lateral, or drift, field component in the electric field produced by the elements of the electrode array which drift field component operates as a mechanism for transferring charge carriers between adjacent wells of the charge couple device. The sloped attitude of the elements of the electrode array is achieved by supporting these elements on sloped portions of the insulation layer. Therefore, in the manufacture of the device, the controlled production of an electrode structure supported by sloped areas of the insulation layer is essential. Furthermore, it was recognized that if adjacent elements of the electrode structure were overlapping, the effective electrical gap between the adjacent elements would be reduced, thereby limiting the formation of surface potential barriers between adjacent wells of the charge couple device such as would inhibit charge transfer between the adjacent potential wells. Furthermore, it was appreciated that it would be desirable to employ a few processing steps as possible to produce the overlapping electrode structure on the insulation layer having selected areas of a controlled slope. Accordingly, there was a need in the prior art for an efficient method of forming an overlapping electrode structure on an insulation layer having selected areas of a predetermined slope.